1. Field of the Invention
This invention generally relates to circuits for producing reference voltages and reference currents, and to time reference circuits which use reference voltages and/or currents to create the time reference, such as oscillators, filters, time delay circuits and clocks, and more specifically relates to a reference circuit which is completely formed as an integrated circuit (i.e., having no external components) and which has either a controlled temperature dependence or substantially no dependence on temperature.
2. Related Art
It is generally desirable for integrated circuits to be fabricated entirely in integrated form (i.e., without any external components or external time references being needed), because an external connection to a component or time reference is a potential source of noise injection or other board or package parasitic problems. The external connection and component also add considerable complexity and significant cost. There are some circuits, however, such as oscillators and filters, which are inherently difficult to fabricate entirely in integrated form, because they require an accurate time constant, and accurate time constants are not readily implemented entirely in integrated form.
Time constants are typically derived from an R-C, L-C or crystal resonator time reference. Crystal resonators cannot be fabricated in an integrated circuit, so use of a crystal resonator inherently involves an external component and connection. Inductors can be fabricated in integrated form, but only in small values as a practical matter, so the use of integrated L-C circuits is limited to high-frequency applications. Internal resistors and capacitors are easy to fabricate in integrated form, but they have inaccurate values with a resulting R-C time constant tolerance in the +/- 30-60% range.
Hybrid circuits have been used to improve on the inaccuracy of integrated R-C time constants. Using an external capacitor improves the tolerance by about 10% and makes big time constants possible, but this becomes unwieldy and expensive if multiple time constants are required. The external connection is also a disadvantage, as noted above, and the inaccuracy of integrated R-C time constants is due mostly to variation of the resistance value with processing and temperature. Since integrated capacitors are usually temperature stable, combining them with an external resistor can yield a time constant accuracy in the range of 15%. It's also easy to use a single master resistor to achieve multiple time constants, but the external connection is still a significant disadvantage. A big jump in accuracy is achieved when trimmed internal resistors having a low temperature coefficient (TC) are used, but unfortunately this results in a big jump in process complexity and product cost.
Perhaps the most popular approach to timing accuracy at this time is to use an accurate external clock for driving switched capacitor circuits. Assuming the availability of such a clock, the system is made more complex by the presence of switching noise and the need for anti-alias and smoothing filters. Continuous-time filters can also be locked to an external clock, but this generally requires an additional phase locked loop (PLL) in the design. Both of these approaches also suffer from the disadvantage of requiring an external connection.
Many applications require an accuracy in timing variation in the range of 5% or better. Accordingly, there is a need for an integrated circuit design for producing a time constant having an accuracy of 5% or better without requiring any external component, clock, or trimming.
In U.S. Pat. No. 4,843,265, a temperature and processing compensated time delay circuit is described which can be fabricated in a monolithic integrated circuit. This circuit is shown in FIG. 1. A bias voltage connected to the gate of a field effect transistor (FET) M.sub.12 is deliberately designed to have a non-linear variation with temperature which substantially matches and compensates for the variation in temperature exhibited by the mobility of the FET, so as to make the drain current of the FET have a value which is not very much dependent upon temperature. The drain current of the FET is then used to discharge a capacitor (not shown) to provide a time constant. This approach promises to achieve the high accuracy desired, but the disclosed circuit implementation still has a number of disadvantages.
The gate bias voltage is given a temperature dependence in this circuit by subtracting three negative temperature coefficient base-emitter voltages (3 V.sub.be), generated by bipolar transistors Q.sub.1, Q.sub.2 and Q.sub.3, from a scaled and temperature-invariant bandgap reference voltage (V.sub.BG). The threshold voltage in FET M.sub.12 is cancelled by level-shifting the gate bias voltage up with another FET M.sub.54. Buffers are used to scale the bandgap reference and to provide a low impedance drive for the current source transistor M.sub.12.
This circuit has the disadvantage that the negative temperature coefficient term cannot be arbitrarily scaled. The coefficient of 3 can be reduced to 2 or increased to 4 by deleting or adding a bipolar transistor to substract or add a base-emitter voltage (V.sub.be), but coefficients in between cannot be selected. This either makes the compensation only approximate (i.e., still leaves a significant temperature variation) or else constrains the drain current of FET M.sub.12 to a single predetermined value that corresponds to the number of V.sub.be voltages subtracted by the circuit.
Another disadvantage stems from the fact that the circuit does not assure that FET M.sub.54 will have its source at the same potential as the source of FET M.sub.12. If the two sources are not at the same potential, the turn on voltages at which the two FETs turn on are not the same and there will not be exact cancellation of the threshold voltage in FET M.sub.12 ! The FIG. 1 circuit also is unduely complex since an operational amplifier A.sub.1 is needed to scale up V.sub.BG and another operational amplifier A.sub.2 is needed to match impedances.
Still another disadvantage is that the FIG. 1 circuit has no way of more accurately matching the temperature variation characteristic of mobility than by the 3 V.sub.be term. This term does not provide an exact match. Furthermore, the circuit is strictly designed for temperature compensating the drain current of an FET connected so as to discharge a capacitor. While this automatically temperature compensates the time delay produced by the capacitor being discharged, there are many other circuit configurations where the time constant will not be temperature compensated properly by the bias voltage dependence on temperature that is created by the FIG. 1 circuit.
One example of a circuit where a different temperature dependence is needed for the bias voltage is in a current source reference or a time reference that uses a current for the reference, such as a transconductance type filter. In this case, the drain current of the FET that needs to be temperature compensated is not proportional to the bias voltage, as is assumed in the FIG. 1 circuit, but instead is proportional to the bias voltage squared. An entirely different temperature dependence is needed for the bias voltage in such a circuit if the time constant is expected to be constant with respect to temperature variation.
There are also situations where it is desired to have a time reference value depend upon temperature, but where the temperature dependence characteristic of mobility in an FET is not the desired temperature dependence characteristic. It would be desirable to be able to arbitrarily tailor the temperature dependence of a time reference (or more generally the temperature dependence of a current source, or the temperature dependence of a bias voltage for an FET).